1. Field of the Invention
This invention relates to analog to digital converters and in particular, sigma delta modulators. In particular, the invention relates to the incorporation of features from sigma delta modulators into converters of the kind known as pipelined or subranging converters, as described hereinbelow.
2. Description of the Prior Art
Sigma delta modulators are described by, for example, Cho and Gray, JSSC March 1995 pp 166-172, and pipelined (also called subranging) converters, described by, for example, Rabii and Wooley, JSSC June 1997 pp 783-795, are used widely for applications where resolutions in the range 10 to 14 bits are required. In certain applications, it is desirable to sample the input signal at a rate higher than the Nyquist rate, to simplify anti-aliasing, or for other reasons. The extent to which the actual sampling rate exceeds the rate specified by the Nyquist criterion is known as the oversampling ratio (OSR). In general subranging converters are preferred where the highest speed of conversions is required and sigma delta converters are preferred for lower speed where a significant level of oversampling is possible.
In the following sections the sigma delta and subranging converters from the prior art are described in more detail. A new structure combining the advantages of sigma delta and subranging converters is then described.
Subranging Converter
A single stage subranging converter (some times called a half flash converter) is illustrated in FIG. 1. It consists of first converter comprising an input signal sampler indicated by Vin at reference 1, a coarse quantizer, (Q1) 2, a digital to analog converter (DAC) 3, a summing node 4, a sample and hold amplifier 5, and a second converter (quantizer Q2) 6. Note that the thin lines in the figures represent analog signals whereas the thicker lines represent digital signals. The input to the DAC 3 comes directly from the coarse quantizer 2. The input signal Vin is quantized by the coarse quantizer 2 at the same time as it is sampled. The output of the DAC 3 is subtracted from the sampled input signal Vin at the summing node 4, ensuring that only a residue, the difference between the input quantizer and a coarse estimate of that input sample Vin, is passed to the sample and hold amplifier 5. This residue will be much smaller than the input signal Vin. For instance, if the coarse quantizer 2 has a resolution of 4 bits, the magnitude of the residues will be limited to {fraction (1/16)} of the maximum magnitude of the input signal Vin. In this residue is passed through the sample and hold amplifier 5 and further quantized by the second quantizer 6. As the input range of this second quantizer 6 is quite small, the second quantizer 6 itself can be quite small. The net effect is that the total quantization is broken down into two steps, coarse quantization and fine quantization, with the final output being obtained from the digital combiner 9 which uses the sum of the two steps (i.e. the sum of the outputs from the two quantizers) with appropriate delays to account for time differences in outputs from the first quantizers and second quantizer for the same input samples. For instance, a net 8 bit quantization can be achieved with a 4 bit coarse quantizer 2 and DAC 3 and a 4 bit second quantizer 6. It may he noted that the summing function 4 dues not require special hardware, and happens automatically at the input to the sample and hold amplifier 5.
Three practical implementation issues may be mentioned. Firstly, it is common practice to design the second quantizer 6 with a range larger than the nominal range of the residue by a factor of 1 bit. This redundancy is referred to as interstage xe2x80x98overlapxe2x80x99. This overlap allows for imperfections in the coarse quantizer 2. Secondly, the DAC 3 must have an accuracy equal to the overall system accuracy, even though this is in excess of the resolution of the DAC 3. Thirdly, it is common practice to provide signal gain in the sample and hold amplifier 5, as this cases the accuracy constraints on the second quantizer 6. Thus, a practical 7 bit subranging converter might consist of two 4 bit accurate 4 bit quantizers 2 and 6, an 8 bit accurate 4 bit DAC 3, and an amplifier 5 with a closed loop gain of 16. There are complex design trade-offs in the choice of amplifier gain, since higher gains result in slower amplifier settling times and hence a lower overall speed of operation. Although, subranging converters are efficient at Nyquist rate sampling, they benefit very little from oversampling.
Where the required resolution exceeds 8 bits, it is common to cascade subranging converter stages. In this arrangement, the second quantizer 6 will itself consist of a subranging converter, so that the quantization is shared over three or more quantizers.
Sigma Delta Modulator
A first order sigma delta modulator from the prior art is illustrated in FIG. 2. It consists of an input sampler at reference 11, the input being Vin, a DAC 17, a summing node 18, a filter means, which in the example shown is an amplifier 15 configured as an integrator, and a coarse quantizer 12. This coarse quantizer 12 will often consist of a single comparator. The input to DAC 17 comes directly from the coarse quantizer 12. The output of the filter means (integrator) 15 is quantized by the coarse quantizer 12, and fed back through the DAC 17 to the summing node 18, where it is subtracted from the input sample Vin. The output from the course quantizer is also the digital output from the sigma delta converter, although further processing may be done on the signal using digital circuitry. Several techniques are known in the prior art to improve the noise performance of sigma delta converters by implementing bit shuffling in the DAC, see for example Irish Patent Nos. 80450 and S970941. Sigma delta modulators are typically operated at a rate much higher than set by the Nyquist criterion. The combination of negative feedback and the signal gain at low frequencies provided by the integrator 15, ensures that the feedback signal matches the input signal Vin at low frequencies. The accuracy of the low frequency matching between feedback and input signals will exceed the resolution of the coarse quantizer 12.
Several other filter means may be used in place of a single integrator, for example two integrators may be used in series. Different filter means may be chosen depending on the required parameters for a given situation, examples of these parameters would include the frequency response of the converter, the Signal to Noise ratio and loop stability of the converter.
A detailed analysis of the operation of sigma delta modulators is complex, see for example, xe2x80x9cDelta-sigma Data Convertersxe2x80x94Theory, Design and Simulationxe2x80x9d, eds. S. R. Norsworthy, R Schreier and G. C. Temes, IEEE Press 1997, ISBN 0-7803-1045-4. However, computer simulations indicate that a first order modulator of the type shown is in FIG. 2, with a 3 bit quantizer 12 and a 3 bit DAC 17, will achieve a resolution of 8 bits, at an oversampling ratio of 64. This resolution will increase by 1.5 bits for every 1 bit increase in the oversampling ratio. If a higher resolution is required at a lower oversampling ratio, then the quantizer resolution must be increased, or a higher order modulator used, as is described in the above-mentioned xe2x80x9cDelta-sigma Data Convertersxe2x80x94Theory, Design and Simulationxe2x80x9d. Alternatively, if a higher oversampling rate is possible, then the quantizer resolution can be reduced while maintaining the same overall system resolution.
Comparison of Sigma Delta and Subranging Converters
It is informative to compare the two foregoing exemplary data converters under the headings of number of quantizers, effect of oversampling, and stage gain.
Number of Quantizers
In the subranging converter of FIG. 1, the quantization is spread over two stages, whereas in the sigma delta modulator, see FIG. 2, all of the quantization must be done in one stage. As, in general, two N/2 bit quantizers require much less circuitry than one N bit quantizer, the subranging converter is preferable from this aspect. A number of prior art sigma delta modulators use multiple quantizers, for example U.S. Pat. No. 4,876,542, U.S. Pat. No. 4,772,871 and U.S. Pat. No. 4,704,600, but these suffer from a number of disadvantages which will be discussed with reference to the invention below.
Effect of Oversampling
In the sigma delta modulator, the resolution increases by 1.5 bits for every increase in OSR by a multiple of two. In the subranging converter, the increase in resolution is only 0.5 bits for every increase in OSR by a multiple of two. Thus the sigma delta modulator is preferable from this aspect. Simulations indicate that this advantage applies as long as OSR greater than 2.
Stage Gain
In the subranging converter, the design of the second quantizer 6 is greatly simplified if the residue signal is amplified. Unfortunately, an amplifier closed loop gain greater than unity increases the amplifier settling time and results in a reduced maximum speed of operation. By contrast, in the sigma delta modulator, the intrinsic operation of the integrator provides signal gain, if OSR greater than 2, so the amplifiers are normally designed with a closed loop gain close to unity. Thus the sigma delta modulator is preferable in this aspect, if OSR greater than 2.
According to the invention, there is provided a novel analog to digital converter for converting an analog input signal to an output digital signal which combines the advantages of subranging and sigma delta structures.
In particular, there is provided an analog to digital converter for converting an analog input signal to a digital output signal, comprising a first converter which comprises a filter means for producing at least one filter output signal by filtering the difference between the analog input signal and a feedback signal generated from a first digital output, a quantizer for producing the first digital output by quantizing the weighted sum of a first filter output from the first filter means and the analog input signal, a second converter for producing a second digital output by converting a second filter output from the filter means, and a digital combiner for combining the first output digital signal and the second output digital signal into the digital output signal.
The digital combiner may include a differentiator for differentiating the second digital output before combining the first digital output and second digital output into the digital output signal.
The digital combiner may include a delay element for delaying the first digital output before combining the first digital output and second digital output into the digital output signal.
The first filter means may comprise at least one integrator. The first filter output and second filter output may be the same.
The digital combiner may include a differentiator for differentiating the second digital output before combining the first digital output and second digital output into the digital output signal
In one embodiment the first filter means comprises two integrators in series, wherein the output of the first integrator is the input to the second integrator and the second filter output is the output of the second integrator. In this embodiment the first filter output may be a weighted combination of the outputs from the first integrator and second integrator. In this embodiment the digital combiner may include a double differentiator for differentiating the second digital output twice before combining the first digital output and second digital output into the digital output signal and/or a delay element for delaying the first digital output before combining the first digital output and second digital output into the digital output signal.
In a further embodiment the second converter comprises a second filter means for producing at least one filter output signal by filtering the difference between the analog input signal and a feedback signal generated from a first digital output, a quantifier for producing the second digital output by quantizing the weighted sum of a third filter output from the second filter means and the analog input signal. In this further embodiment, a third converter may be provided for producing a third digital output by converting a second filter output from the second filter means, and the digital combiner includes means for combining the third digital signal with the first output digital signal and the second output digital signal into the digital output signal. The digital combiner may include delay elements for delaying the first digital output and second digital output before combining the first digital output, second digital output and third digital output into the digital output signal and/or a differentiator for differentiating the second digital output and a double differentiator for differentiating the third digital signal before combining the first digital output, second digital output and third digital output into the digital output signal.